In general, semiconductor materials may be processed in semiconductor technology on or in a substrate (also referred to as a wafer or a carrier), e.g. to fabricate integrated circuits (also referred to as chips). During fabricating integrated circuits, certain processes may be applied, such as doping the semiconductor materials, planarizing the substrate, forming one or more layers over the substrate, structuring the one or more layers, or contacting the readily fabricated chips.
Conventionally, planarizing uses a chemical polishing process and/or mechanical polishing process. Due to quality criteria, adapting the setup of this process to various technologies, various wafer diameters and various wafer (e.g., silicon) thicknesses may be difficult. Further, the process parameter window may be very narrow, which increases the effort for aligning the process of multiple tools such as to increase reproducibility.
In several processes, the used materials may chemically react with each other and may be, depending on their phase diagrams, converted into parasitic phases, such as precipitates, inclusions, mixed crystals and allotrope modifications, e.g., in micrometer scale. Those parasitic phases may differ in their mechanical and chemical properties from the primary phase, and therefore may complicate the planarizing. For example, a mechanically and/or chemically stable parasitic phase may be resistant against the planarizing.
By way of example, PtxSiy grains may form at the front side of the substrate. FIG. 1A illustrates PtxSiy grains 102 on a substrate surface, which appear darker in the microscopy image. Conventionally, there may be no planarization process applicable for removing the PtxSiy grains without damaging the substrate. Thus, the PtxSiy grains are conventionally overgrown by following layers, e.g., by electroless plating (also referred to as e-less plating). For example, the PtxSiy grains may be covered by an AlSiCu layer, which may be subsequently covered by NiP plating. During the e-less plating process, the AlSiCu layer proximate the PtxSiy grains may be etched away, e.g., in particular for extraordinarily large scale PtxSiy grains. The resulting recess in the AlSiCu layer may lead to an inhomogeneous NiP plating 104 proximate the PtxSiy grains (e.g., leading to optically detectable defects). FIG. 1B illustrates a resulting inhomogeneity 104 in a top view and cross sectional FIB (focused ion beam) image. The resulting inhomogeneities 104 increase the risk of malfunction of the readily fabricated chip and reduce its reliability.
By way of example, PtxSiy grains may form at the backside of the substrate. The backside may be conventionally planarized by a chemical polishing process, e.g., for thinning the substrate. However, the chemical polishing process may be limited in reducing the surface roughness, since the PtxSiy grains may be resistant against the chemical polishing process. In other words, the PtxSiy grains may remain unmodified during the chemical polishing process. However, if the applied mechanical force is high enough, the PtxSiy grains may be torn out of the substrate (e.g., made from silicon) resulting in a nonsymmetrical recess in the substrate (illustratively, a “crater”). FIG. 2A is a microscopy image that illustrates nonsymmetrical recesses 202 in a substrate, which appear darker in the microscopy image. The remaining surface roughness may increase through metal diffusion into the substrate (e.g., during forming a backside metallization) and, thereby, reduce the solderability (e.g., for die attach) and/or increase the risk of peeling off (e.g., at a pick up process). FIG. 2B illustrates metal diffusion related inhomogeneities 204 as well as voids 206 in a metallization. The resulting inhomogeneities 204 and voids 206 increase the risk of malfunction of a readily fabricated chip and reduce its reliability.